//****************************************************************************
//                      iic_comm
//
//功能：测试单bit输入信号
//
//版本:
//iic_comm_X01	ZGragon       2021/06/23
//					
//****************************************************************************

module iic_comm(
    //CLK & Reset
	input                   iSysClk             ,// 50M or lower
	input                   iSysRstN            ,// active high
    //IIC
    input   [6:0]           iSlvAddr            ,// Slave Address
    input                   iSerSel             ,// Serial line select (0:Disable 1:Enable)
    input                   iSCL                ,// IIC Serial Clock

    input                   iSdaI               ,// IIC Serial Clock
    output                  oSdaO               ,// IIC Serial Output
    output                  oSdaOE               // IIC Serial Output enable (1:HiZ 0:Output)
    //input  REG

    //output REG
);

//程序版本信息
parameter	main_function	=  "F"  ;//"F"    
parameter	sub_function	=  "T"  ;//"T"    
parameter	main_solution	=  8'd1 ;//"1"    
parameter	sub_solution	=  8'd1 ;//"01"   
parameter	application_type=  "G"  ;//"G"    
parameter	main_version	=  8'd1 ;//"01"   
parameter	sub_version		=  8'h84;//"C04"
parameter	mini_version	=  8'd6 ;//"06" 
parameter	years	        =  8'd21;//"06" 
parameter	months	        =  8'd6 ;//"06" 
parameter	days	        =  8'd22;//"06" 

(*keep*)wire        WrEn    ;
(*keep*)wire        RdEn    ;
(*keep*)wire [15:0] Addr    ;//1个地址4个byte数据
(*keep*)wire [31:0] WrData  ;
(*keep*)reg  [31:0] RdData  ;

//test wr 
(*keep*)reg  [7:0]  iic_reg0;
(*keep*)reg  [7:0]  iic_reg1;
(*keep*)reg  [7:0]  iic_reg2;
(*keep*)reg  [7:0]  iic_reg3;

IIC_IF 
    IIC_IF_U(

	.RST        (~iSysRstN  ),// async. reset
	.CLK        (iSysClk    ),// clock 50MHz

	.SLV_ADR    (iSlvAddr   ),// Slave Address
	.SER_SEL    (iSerSel    ),// Serial line select (0:Disable 1:Enable)
	.SCL        (iSCL       ),// IIC Serial Clock
	.SDA_I      (iSdaI      ),// IIC Serial Input
	.SDA_O      (oSdaO      ),// IIC Serial Output
	.SDA_OE	    (oSdaOE     ),// IIC Serial Output enable (1:HiZ 0:Output)

	.REG_RD     (RdEn       ),// REG I/F read enable
	.REG_WR     (WrEn       ),// REG I/F write enable
	.REG_ADDR   (Addr       ),// REG I/F address
	.REG_WDAT   (WrData     ),// REG I/F write data
	.REG_RDAT   (RdData     ) // REG I/F read data
) ;

//decode
always @(posedge iSysClk or negedge iSysRstN) 
    if(!iSysRstN)begin 
        iic_reg0  <= 8'd0;
        iic_reg1  <= 8'd0;
        iic_reg2  <= 8'd0;
        iic_reg3  <= 8'd0;
    end 
    else if(WrEn)begin 
        case(Addr)
        12'h000:begin 
                    iic_reg0  <= WrData[31:24];               
                    iic_reg1  <= WrData[23:16];
                    iic_reg2  <= WrData[15: 8];
                    iic_reg3  <= WrData[7 : 0];
                end
        endcase 
    end 

//encode
always @(posedge iSysClk or negedge iSysRstN)begin 
    if(!iSysRstN)begin 
        RdData <= 'd0;
    end 
    else if(RdEn)begin
        case (Addr)
            12'h000:RdData <= {main_function,sub_function,main_solution,sub_solution};//{01,01,T,F}
            12'h004:RdData <= {application_type,main_version,sub_version,mini_version};//{06,00,01,G}
            12'h008:RdData <= {years,months,days,8'd0};//

            default:RdData <= 'd0    ;
        endcase
    end 
end  

endmodule